With rapid development of semiconductor fabrication technology, semiconductor devices are developed towards a direction of having a higher component density and a higher integration degree. As one of the most fundamental semiconductor devices, transistors have been widely used. With the improvement of the component density and the integration degree, the size of the gate electrode in planar transistors becomes smaller and smaller. However, as the feature size decreases, the ability of traditional planar transistors in controlling the channel current becomes less sufficient, which may cause short channel effect and leakage current, and thus may ultimately affect the electrical performance of the semiconductor devices.
According to existing methods, fin-field effect transistor (Fin-FET) has been proposed in order to overcome the short channel effect and suppress the leakage current. A Fin-FET may be a multi-gate device.
As an example, a Fin-FET may include a substrate, a fin structure formed on the surface of the substrate, a dielectric isolation layer formed on the surface of the substrate and covering a portion of the sidewall surfaces of the fin structure, a gate structure formed on the surface of the dielectric isolation layer and the top and the sidewall surfaces of the fin structure, and a source region and a drain region formed in the fin structure on the two sides of the gate structure. The gate structure may include a gate dielectric layer formed on the surface of the dielectric isolation layer and a portion of sidewall and top surfaces of the fin structure, a gate electrode layer formed on the surface of the gate dielectric layer, and two sidewall spacers formed on the sidewall surfaces of the gate electrode layer and the gate dielectric layer. Moreover, conductive structures, such as conductive plugs and electrical interconnections, may be formed on at least one of the source region, the drain region, and the gate electrode layer of the Fin-FET in order to electrically connect the Fin-FET with other semiconductor components on the substrate to further form a chip circuit.
However, as the process node shrinks, the size of Fin-FETs decreases and the density of devices increases. Therefore, the fabrication process for Fin-FETs becomes more difficult and the electrical performance of the formed Fin-FETs still needs to be improved. The disclosed fabrication method and semiconductor device are directed to solve one or more problems set forth above and other problems in the art.